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? semiconductor components industries, llc, 2003 october, 2003 ? rev. 0 1 publication order number: and8129/d and8129/d a 30 w power supply operating in quasi-square wave resonant mode prepared by: christophe basso on semiconductor introduction quasi?square wave resonant converters, often noted qr converters, of fer an elegant means to make flyback supplies look more friendly on the electro?magnetic interference (emi) point of view. by delaying the on switching event until the drain?source voltage has decayed to a minimum, switching losses are reduced and rising slopes lose their stiffness. designers get an immediate benefit from this configuration since the mosfet runs cooler and the emi input filter becomes easier to implement. designing qr switch?mode power supplies (smps) requires some attention but is not an area dedicated to experts only. you will discover through the following lines how new on semiconductor solutions can help you to quickly turn your quasi?resonant project into a working device. what is quasi?resonance? the term quasi?resonance is normally related to the association of a real hard?switching converter and a resonant tank. while the operation in terms of control is similar to that of a standard pwm controller, an additional network is added to shape the variables around the mosfet: current or voltage. depending on the operating mode, it becomes possible to either switch at zero current (zcs) or zero voltage (zvs). compared to a conventional pwm converter, a qr operation offers less switching losses but the rms current circulating through the mosfet increases and forces higher conduction losses. however, one of the main advantage in favor of the quasi?resonance is the reduced spectrum content either conducted or radiated. true zvs quasi?resonance means that the voltage present on the switch looks like a sinusoidal arch. figure 1 shows how such a signal could look. figure 1. a truly resonating vds signal on a quasi?resonant flyback converter 230 170 110 50 ?10 1.69u 1.73u 1.77u 1.81u 1.85u ip lf ctot the main problem with this technique lies in the very high voltage generated at the switch opening. most of the time, these resonant offline designs require around 1.0 kv bvdss mosfets whose price is clearly incompatible with high volume markets. as a result, designers orientate their choice toward another compromise called quasi?square wave resonant power supplies. quasi?square wave resonant converters as we saw, true resonant operation hampers the mosfet selection by imposing a high voltage at the switch opening. if we closely look at the standard hard?switching waveform (figure 2), we can see that there exists a time where the drain voltage gets minimum. this occurs just after the core reset. application note http://onsemi.com
and8129/d http://onsemi.com 2 drain voltage 1 2 lleak ctot drain current vds is minimum ip core is reset 1 2 lpctot figure 2. hard?switching waveforms in discontinuous conduction mode (dcm) from figure 2, it is possible to imagine a controller that turns a mosfet on until its current grows?up to the setpoint to turn it off and then waits until the core reset is detected (usually via an auxiliary winding) to reactivate this transistor. as a result, the controller does not include any standalone clock but only detects the presence of events conditioned by load/line conditions: this is a so?called free?running operation. converters based on this technique are often designated as self?oscillating power supplies (sops), valley switching converters, etc. oscillations origins can be seen from figure 3 arrangement where l?c networks appear. depending on the event, two different configurations are in play: ? at the switch closing, the primary current crosses the primary inductance but also the leakage inductance, lleak. when the turn?on time expires, the energy stored in lp is transferred to the secondary side of the transformer via the coupling flux. however, the leakage inductance, which models the coupling between both transformer sides, reverses its voltage and imposes a quickly rising drain voltage. the slope of this current is ip ctot (eq. 1) where ctot lumps all capacitances surrounding the drain node: mosfet capacitors, primary transformer parasitics but also those reflected from the secondary side etc. as a result, lleak and ctot form a resonating network of natural frequency 1 2 lleak ctot (eq. 2 ) . the maximum drain voltage can then be computed using the characteristic impedance of this lc network. vds max vin 1 n (vout vf) ip leak ctot (eq. 3) figure 3. a typical flyback arrangement unveils two different resonating networks 1.005m 1.015m 1.025m 1.035m 1.045m ?100 100 300 500 700 t valley t = 0 () vf vout n + ? 1 () vf vout n + ? 1 vin multiple valleys e t lp rp ? ? - 2 + vin drv ctot vds lleak rp 1:n + vout figure 4. a typical flyback ringing waveform occurring at the switch opening lp
and8129/d http://onsemi.com 3 ? when the transformer core resets, primary and secondary currents drop to zero: the secondary diode stops its conduction and the reflected voltage on the primary naturally dies out. from eq. 3, this implies that the terms after vin all collapse to zero and vds tends toward vin. however, the transition would be brutal in the lack of a resonating network, this time made by lp, the primary inductance, and nearly the same ctot as before. as you can imagine, a sinusoidal ringing takes place, damped by the presence of ohmic losses (dc + ac resistance of the primary winding modeled by rp). the drain?source shape rings as the below formula details: vds(t) vin 1 n (vout vf) e ? t (eq. 4) cos(2 fprimt) with: rp 2lp (eq. 5) (the damping factor), fprim = 1 2 lpctot (eq. 6) (natural ringing frequency), vin is the input voltage, vf the diode's forward drop and n, the ns:np turn ratio. we can see from figure 4 that the drain is the seat of various voltage drops when going down the ringing wave. these drops are called avalleyso. if we manage to switch the mosfet right in the middle of these valleys, we ensure minimum turn?on losses, particularly those related to capacitive dissipation: pavg cap 1 2 ctotvds 2 fsw (eq. 7) 0. thus, quasi? square wave operation or valley switching, will imply a reactivation of the switch when vds is minimum. as various figures portray, this occurs some time further to the transformer core reset. by implementing this method, we build a converter which naturally exhibits a variable frequency operation since the reset time depends upon the input/output operating conditions. figure 5 shows a typical shot of a quasi?square wave converter. figure 5. a typical drain?source shot of a quasi?square wave converter figure 6. the primary inductance current is made of two different slopes (here a restart occurs on the second one) 1 st valley ipeak s = vin / lp s = n . (vout + vf) / lp on off 0 ip = 0 as one can see, the total period is made of dif ferent events, where the core is first magnetized (ton), then fully reset (toff) and finally a time (tw) delay is inserted to reach the lowest value on the drain. let us look at how the frequency moves by respect to the input/output conditions. evaluating the free?running switching frequency the free?running frequency can be evaluated by looking at figure 6, where the primary current (circulating in the primary inductance) is depicted. from the definition of the various slopes, we can express the first two events, ton and toff quite easily: ton lp vin dc ip (eq. 8) toff lp np ns (vout vf)
ip (eq. 9) for the tw event, which is one fourth of the natural ringing frequency given by equation 4, we will compute the derivative of equation 4 and null it to find its minimum: d(vin e (? t) cos(2 fprimt)) dt 0 (eq. 10) which gives a result of: tw 1 2ft 1 2 tan 2 fprim
fprim (eq. 11) however, this result is not very practical because of its inherent complexity. if we observe equation 10, we can see that the minimum is reached when the term cos(2 fprimt) equals ?1. otherwise stated, we can solve t for which the cosine is null or the full product equals . this gives: tw 1 2fprim lpcp (eq. 12)
and8129/d http://onsemi.com 4 however, this result is valid only for low damping coefficient, that is to say, e ? t 1 . experience shows that it is good enough for the vast majority of cases. as a result, the final switching period is computed by summing up all these sequences and introducing the input power expression: tsw ton toff tw (eq. 13) ton toff tw ip lp 1 vin dc 1 np ns (vout vf)
lpcp 1 fsw (eq. 14) pin pout 1 2 lpip 2 fsw (eq. 15) ip 2 pout lp fsw (eq. 16) from eq. 15, now, plugging fsw (eq. 14) in eq. 16, gives: ip lp 1 vindc 1 vreflect tw lp ip 2 pout2 (eq. 16a) with: vreflect = np ns [vout vf] tw = lpcp the converter efficiency pout the output power vout and vf, respectively the output voltage and the rectifier drop @ id = iout lp the primary inductance stating that lp x pout = a: ip a vreflect avin a (a vreflect 2 2 a vreflect vin avin 2 2 vin 2 vreflect 2 tw)

( lp vin vreflect) (eq. 17) from equation 16, one can then compute the switching frequency using the calculated peak current: fsw 2 pout lp ip 2 (eq. 18) however, equation 17 is not very practical since it involves lp, what we are actually looking for. it can certainly be used to discover the operating peak current from known inductance and capacitor values but neglecting tw, offers a simpler formula that can be used as first frequency iteration (e.g. to feed a spice simulator for instance): fsw 1 lp 2 pout n (vout vf) vin ( (vin(n(vout vf)))) 2 (eq. 19) entering equation 18 into a spreadsheet and plotting fsw versus various parameters (vout, iout etc.), it gives an idea about the high frequency variability of the system. figure 7 and figure 8 respectively plot fsw in function of the input voltage and the output current for a given application. figure 7. frequency variations for a 100 w smps operated from universal mains figure 8. frequency dependency with load at a given input voltage (100 v) vindc 400 350 300 250 200 150 100 f(vindc) 7*10 4 6*10 4 5*10 4 4*10 4 3*10 4 2*10 4 1*10 4 po, output power (w) 100 80 60 40 20 0 f(po) 2*10 5 1.5*10 5 5*10 4 1*10 5 0
and8129/d http://onsemi.com 5 figure 9. peak current variations for a 100 w output power with different line voltages vindc 400 350 300 250 200 150 100 ip(vindc) 3.5 3 2.5 2 1.5 a quiet emi signature manipulating sinusoidal (or close?to) variables always offer a narrower spectrum content compared to hard?switching systems. figures 10 and 11 depict the conducted emi signature of two systems operated at the same point but implementing different switching techniques. figure 10. a soft?switching approach reduces the energy content above 1.0 mhz . . . figure 11. . . . while a hard?switching system generates a lot of noise in this portion since the mosfet is reactivated at the lowest drain level, the classical coss capacitor discharge at the switch closing is non?existing and the very narrow peak current has gone (also this peak is often confusing the current?sense comparator when it is really energetic, even sometimes despite the presence of the leb circuitry). as a result, quasi?square wave converters are recommended where the switch?mode power supply (smps) needs to operate close to radio?frequency section, e.g. set top boxes, tv sets, etc. detecting the core reset event core reset detection is usually done via a dedicated auxiliary winding whose voltage image is directly linked to the transformer flux by vaux n d dt (eq. 20) . depending on the controller device, the polarity of the observed signal must fit its detection circuitry. in on semiconductor ncp1205, this polarity should be of forward type, that is to say, when the mosfet opens, the auxiliary voltage (actually the flyback level) dips below ground and stays there, safely clamped at 0.7 v, until the core reset occurs. figure 12 gives an example of a demagnetization signal given by an auxiliary winding wired in both types.
and8129/d http://onsemi.com 6 figure 12. core reset detection signal coming from either a forward or flyback winding ? 20.0 ? 10.0 0 10.0 20.0 ? 20.0 ? 10.0 0 10.0 20.0 forward operation flyback operation 65mv ? n.vin n.vin watch out for possible re? start! leakage contribution operating the auxiliary winding in forward of fers various advantages as the use of the variable vcc level to introduce overpower compensation. also the controller is always operating (supplied) whatever the secondary output conditions. figure 14 shows a possible way to do that. please note the presence of a small rc filter necessary to a) introduce a time delay after the core resets (and thus activate the mosfet right in the minimum of the valley wave) b) to filter out any leakage contribution that could adversely restart the controller at a higher switching frequency (see figure 12 evidence). overpower compensation is there to avoid a larger over current trip point at high?line compared to low?line conditions. for instance, suppose that the maximum peak current at low line (100 v) would be 3.3 a to pass 100 w and that your maximum peak current (given by the sensing element and the internal clamping setpoint, usually 1.0 v) is fixed to 4.0 a. it means that the overcurrent condition exists as soon as the output load slightly increases, perhaps to 120 w, which is what was defined with a maximum peak of 4.0 a. now, if you run the converter at high line, e.g. 350 vdc, the peak current will decrease, as shown by figures 9 thru 14, down to 1.8 a. as a result, you still have a dynamic of 2.2 a to go before hitting the 4.0 a maximum current trip point. the smps can thus theoretically deliver up to 220 w before it actually trips. to overcome this problem, you can wire a resistor between the vcc and the current sense pin since, in forward polarity, vcc naux np vin dc (eq. 21) which is a direct image of the mains. as a result, vcc moves with the high?voltage rail and offsets the current sense reading, offering a natural, low power, input feedforward.
and8129/d http://onsemi.com 7 figure 13. quasi?resonant applications impose different operating peak current depending on the input line. + vout hv r c + rlimit demag vcc aux drv cs 1 k overpower figure 14. wiring the auxiliary in forward mode offers the ability to build an inexpensive overpower compensation since vcc aux. moves with the input voltage. max ip low line operation max ip high line operation care should be taken however, to not inject too much over power level into the cs pin otherwise it may affect the vco operation. in some applications, it is difficult to cope with a variable auxiliary level and a flyback option is better. + vout hv r c + rlimit demag vcc aux drv cs rsense figure 15. wiring the winding in flyback mode is also possible with the ncp1205 by adding a second diode, it becomes easy to wire the auxiliary winding in flyback mode, but still offering a core reset signal in the forward polarity. figure 15 offers an example, where the demagnetization signal undergoes a high?frequency filtering via a rc network. the ncp1205 quasi?resonant controller this ncp1205 available in dip8, dip14 and so?16, offers many features that make it the right candidate in quasi?resonant applications: ? full quasi?square wave resonant operation: by detecting the end of the transformer core demagnetization to initiate a new cycle, the ncp1205 ensures drain?source valley switching or qr operation. furthermore, due to comprehensive logic circuitry, the device jumps between the valleys as the built?in vco starts to decrease the switching frequency. as a result, electromagnetic? interference (emi) are reduced and turn?on losses are virtually null. ? voltage?controlled oscillator: an internal vco takes over as soon as the free?running frequency hits a maximum user adjustable value. as the output power demand further diminishes, the switching frequency is naturally reduced to ensure a better efficiency at light loads.
and8129/d http://onsemi.com 8 ? low standby power: if smps naturally exhibits a good efficiency at nominal load, they begin to be less efficient when the output power demand vanishes. by smoothly reducing the number of switching cycles per second, the ncp1205 drastically reduces the power wasted during light load conditions. in no?load conditions, the ncp1205 allows the total standby power to easily reach and exceed the next international energy agency (iea) recommendations. ? short?circuit protection: by permanently monitoring the feedback line activity, the ic is able to detect the presence of a short?circuit, immediately reducing the output power for a total system protection. once the short has disappeared, the controller resumes and goes back to normal operation. for given applications, you can easily disconnect this protective feature. this short?circuit detection is independent from the auxiliary level, hence a lose coupling between auxiliary and power windings is not a problem. ? overvoltage protection: by continuously checking its own vcc rail, the ncp1205 can safely go into latch?off phase when the operating voltage exceeds 36 v. in forward winding applications, this options lets you also protect the design against transient mains over voltages. for application where an adjustment is necessary, the dip14 versions pins out the dedicated comparator input to let you select the protection level of your choice. ? large supply range: battery charger applications require that the controller can still control the output current when the output voltage is close to zero (e.g. a discharged battery). this is called constant?current/ constant?voltage (cc?cv) operation. to allow the controller self?supply when the output voltage disappears, one needs to wire the auxiliary winding in the forward mode. however, most of today's primary side controllers have difficulty to cope with a forward auxiliary winding operated on a universal mains because of the large voltage dynamics it implies. fortunately, by authorizing 7.0 v through 36 v operation, the ncp1205 eases the designer task on the self?supply side. ? low output ripple in standby: some loads are sensitive to the ripple present on the output. this is the case for li?ion batteries where a clean voltage is required to ensure the longest service. standard hysteretic controllers produce un?acceptable output ripple. by smoothly reducing the operating frequency, the ncp1205 generates a lower ripple when entering the standby mode. ? no acoustic noise while operating: instead of reducing the switching frequency at high peak currents, the ncp1205 waits until the peak current demand falls below a fixed 1/3 rd of the peak maximum limit. as a result, frequency reduction takes place without having a singing transformer. you can thus select cheap magnetic components free of noise problems. ? external mosfet connection: by leaving the external mosfet external to the ic, you can select avalanche proof devices which, in certain cases (e.g. low output powers), let you work without an active clamping network. also, by controlling the mosfet gate signal flow, you have an option to slow down the device commutation, therefore reducing the amount of electromagnetic interference (emi). ? spice model: a dedicated model that lets you run transient cycle?by?cycle simulations is available to verify your theoretical design. ready?to?use templates can be downloaded in orcad's pspice and intusoft's from on semiconductor web site, ncp1205 related section. complete details regarding the implementation of the ncp1205 are given in the application note and8043. a 30 w power supply design using the quasi?resonant approach pout nominal = 30 w vout = 16.8 v universal input voltage = 90265 vac vdc min 100 vdc (including losses and ripple) vdc max 370 vdc short?circuit protection standby power less than 300 mw at no?load the design of a quasi?resonant converter featuring low standby power requires the understanding of several parameters before calculating anything: 1. do we need to ensure true zero voltage switching (zvs) operation over a large operating input range? 2. if we ensure high switching frequency at maximum power and low mains, while it minimizes the magnetics, the frequency foldback will eventually take place at higher input voltages. 3. at what peak current level do we authorize the frequency foldback to avoid acoustical noise in the transformer? answer 1: yes, because we will shape the drain?source voltage (especially at the switch opening) to be as smooth as possible to a) soften the emi signature b) wire a large resonating capacitor whose losses should be minimized (see eq. 7) c) due to b, we will save a costly rcd clamping network. as a result, we will reflect as much as we can, taking into account a 800 v bvdss mosfet and higher secondary rectifier losses (peak and rms secondary currents go up). we have selected a turn ratio of 16.6 who gives a reflected voltage of 288 v. the drain stress at high line without leakage, is thus: (265 x 1.414) + 288 = 662 v, which gives room for the leakage effects. please remember that the best is to reflect the maximum voltage from the secondary side, best case being vreflect = n x (vout + vf) = vin. but in that
and8129/d http://onsemi.com 9 latest case, you would probably need to pick up a 900 v or 1.0 kv bvdss mosfet. answer 2: in our case, we prefer to avoid any foldback at nominal load over the whole input voltage. frequency foldback starts by discrete jumps between valleys and can create some noise. if we accept to increase the frequency at high line before folding the frequency back (with a 1.0 nf connected to pin 4, we clamp at fmin = 90 khz), then we can accept to lower the switching frequency at low lines, but not too low to avoid entering audible frequencies. answer 3: the answer really depends upon the transformer structure you have used, e.g. the type of core, bobbin, etc. the best is to setup a test structure where you impose a peak current in your transformer prototype at low, audible, frequency (e.g. around 5.0 khz). figure 16 offers a possibility to do that via a power mosfet. 1 figure 16. a power mosfet and an adjustable duty?cycle generator lets you select the right peak current. 1 2 current reading 3 pulse 4 + vin by adjusting the pulse source duty?cycle, it becomes possible to impose a given peak current, directly sensed across the 1.0 resistor via an oscilloscope. the freewheel diode could be a 1n4937/mur160 or equivalent whereas the source vin can be around 30 vdc with a 100 v bvdss 6.0 a mosfet. start by low peak currents and slowly increase the duty?cycle until noise can be heard. this corresponds to the very maximum peak current you can pass while skipping cycles or when entering frequency foldback without having a singing transformer. the best is actually to generate burst of pulses to drive the mosfet. the discontinuity associated with the burst sequence is more favorable to trigger mechanical resonances compared to evenly spaced pulses. suppose that a 550 ma peak current is offering the best value with your transformer. since the 1205 folds back at 30% of the maximum primary current, you will select a maximum peak current of 1.0 v/1.65 a or an rsense of 0.6 . iterations using the dedicated excel spreadsheet will therefore help to select the right primary inductance and turns?ratio to reach good performance in standby without making noise. let's now follow the below design steps to build our 30 w qr switch?mode power supply: 1. in our opinion, the very first element to dimension is the primary to secondary turn ratio. in effect, it will condition, among other parameters, a) the drain?source stress of the mosfet at its opening b) the peak inverse voltage (piv) of the secondary rectifier at the switch closing c) the area where the supply operates in zero voltage switching (zvs). as we have seen before, if we select an 800 v mosfet, we can select the turn ratio by (including a 10% safety margin): max vin dc np ns (vout vf) 800 v?10% (eq. 22) np/ns 19.5. we selected a 16.6 turn?ratio which will ensure zvs up to vin = 16.6 x (16.8 + 1) = 295 vdc. 2. having the right turn ratio, we can calculate the primary peak current needed to pass the 30 w of power. if we neglect the delay to reach the valley of vds(t) (see eq. 12), then we end up with a simplified current definition: ip max 2 pout np ns (vout vf) min vin dc min vin dc np ns (vout vf) plugging values into it gives us a maximum peak current of: 0.94 a. this value will slightly change as soon as you consider other parasitic elements (see and8089, adetermining the free?running frequency for qr systemso), but is a good starting point. 3. from that value, we know that the ncp1205 will start folding back the frequency into the audible range at a peak current equal to 30% of the maximum value (this is the way the ncp1205 is designed). we know by experience (see figure 16), that we shall not go over 550 ma to avoid having a singing transformer. in our case, 30% of 0.94 a is well within our specs. we even have place for improvement if we feel a need to increase ip max for parameter variation reasons.
and8129/d http://onsemi.com 10 4. the inductor is defined knowing what frequency range we want to cover. as exemplified by figure 16, the switching frequency increases at high input voltage (whereas ip goes low) and decreases at low input voltages (whereas ip goes up). in some cases, it is desirable to keep the magnetics small and thus operate at high frequency at low line. on the other way, some designers find that is desirable to compensate the higher rms losses at low line, by reducing the switching losses via a lower switching rate. we will stick for this latest option and calculate lp to be above the audible range at low line and maximum output power. rearranging equation 19, leads to solve: lp 1 fsw min 2 pout np ns (vout vf) vin min vin min np ns (vout vf) 2 (eq. 23) or lp greater than 1.9 mh. this number is a first result and we will see that further iterations are needed to freeze this number. 5. since we implement true zvs up to 295 v, we can connect a large capacitor between drain and ground to clamp the maximum voltage generated by the leakage inductance. the v 2 capacitor losses will be null in zvs (see eq. 7) but will start to increase at high line when zvs is lost. we believe that even if it is a bit detrimental to efficiency, the cost improvement brought by the absence of a rcd clamping network and smoother waveforms (good for emi), really justifies the addition of this drain?ground capacitor. by tweaking equation 3, we can calculate the amount of necessary capacitance we need between drain and ground: creso lleak vds max ?vin? np ns (vout vf) 2 ip 2 (eq. 24) if we consider a leakage inductance of around 30 h (first estimation) and we plug our values into equation 24, then creso needs to be greater than 1.6 nf. by losing zvs at 295 v, we can imagine that the switch restart will occur on a drain wave at 330 v?295 = 35 v. these nominal conditions imply a theoretical switching frequency of 131 khz (eq. 19) and capacitive losses of (eq. 7): ploss = 0.5 x 35 2 x 1.6 n x 131 k = 130 mw which is acceptable. 6. you can see through the lines we wrote that many parameters can be changed to obtain different converters at the end. the reflected voltage is obviously one of the most sensitive parameters which influences others. increasing the reflected voltages to keep a wider zvs operating range has a price on other numbers: the switching frequency increases (reset voltage on lp is stronger) the primary peak current and conduction losses are improved (if fsw goes up, the peak demand goes low) the secondary peak current and conduction losses increase the mosfet undergoes a bigger stress at the switch opening mosfet turn?on losses can be really null (if zvs is achieved) 7. final values will be obtained due to the design spreadsheet available to download from on semiconductor web site which includes parasitic elements (such as the leakage inductance and the cds capacitor) and whose formulae are described in and8089. after we entered our desired operating conditions, the below numbers were extracted from the spreadsheet: lp = 1.2 mh lleak (measured) = 15 h np/ns = 16.6 ip max = 1.5 a, to include various tolerances rshunt = 2 x 1.2 in parallel creso = 1.5 nf/1.0 kv calculated frequency at nominal load and minimum input voltage = 50 khz (120 vdc and 30 w) calculated frequency at nominal load and maximum input voltage = 87 khz (370 vdc and 30 w) using spice to check for the validity of the assumptions despite the existence of a dedicated ncp1205 spice model, it is faster and easier to use a simplified free?run approach to have an idea of the final results. figure 17 of fers a possible way to represent a free?running controller: the demagnetization path includes a standard flip?flop which latches the transition while the feedback signal fixes the current setpoint. due to a simple arrangement, the system simulates really quickly and allows an immediate assessment of what has been suggested by the excel spreadsheet. the feedback loop is purposely simplified with a zener diode arrangement, but you can upgrade it with a tl431 circuitry. it will simply take longer simulation time to settle. as figures 18 and 19 show, it is difficult to make the distinction between the simulation and the real measurement on the demoboard.
and8129/d http://onsemi.com 11 figure 17. a simplified free?running controller eases the simulation setup and increases speed 18 5 3 4 7 6 2 + vin 360 r1 22 k dem x2 free run dt fb free run id rsense 0.5 + vdrain ireso creso 1.5 n lleak 15 u vcoil icoil lprim 1.2 mh dem c6 330 p x1 mbr20100 idiode resr1 60 m cout1 2.2 mf ic = 16 iout vout vout rload 9.4 ++ x4 xfmr?aux ratio_pow = ?0.06 ratio_aux = 0.06 rprim 0.5 c5 10 n feedback fb vout rled 1 k x7 moc8101 d4 bv = 15.6 r6 5.6 k
and8129/d http://onsemi.com 12 figure 18. figure 19. it becomes difficult to differentiate the simulation from the real world . . . figure 18 is simulation, figure 19 is measured. vds = 200 v/div x = 3 s/div vsense = 200 mv/div the spice simulation offers another advantage which is the evaluation of the component stresses. due to good models, you can immediately measure the mosfet conduction losses worse case, the rms current in the rectifiers, in the resonating capacitor, etc. figure 20 portrays these typical waveforms. in light of this data, we can now select components and peripherals accordingly: mosfet: depending on the type, you compute the power using: pconduction = rds(on) @ tj = 100 c x idrms 2 = 3 x 0.465 2 = 650 mw at low line. in our case, switching losses are close to zero due to zvs and zcs. when the main grows up to 370 vdc on the bulk capacitor, the zvs effect goes away and capacitive losses appear due to creso. simulation shows that conduction losses stay below 1.0 w. we selected an 800 v mosfet from st. a small note about mosfet spice models: they do not reflect tj temperature effects on the rds(on) and other parameters (e.g. vth). as a result, calculating the total power (including switching losses) by multiplying and averaging vds(t) x id(t) over one period does only make sense for junction temperatures of 27 c. resonating capacitor: this device shall sustain the voltage peak but also a large rms current. simulations show that worse case occurs at high line with a rms current of 370 ma. we have used a wima fpk1 series with good results. primary inductance: low line imposes the highest stress on the transformer. the following specs to be passed to the transformer manufacturer: lp = 1.2 mh ipmax = 2.0 a iprms = 571 ma np:ns = 1:0.06 np:naux = 1:0.06 secondary rectifier: the conduction losses of a diode are given by: p = idrms 2 x rd + vf @ id x idavg. in our case, we obtain theoretical total losses of 1.21 w. an mbr10100 can be a good choice.
and8129/d http://onsemi.com 13 1 id 2 icoil 3 idiode 4 ireso 5 i(cout1) ?400m 0 400m 800m 1.20 id in amperes plot1 1 ?400m 0 400m 800m 1.20 icoil in amperes plot2 2 434m 7.51 14.6 21.6 28.7 idiode in amperes plot3 3 ?600m ?200m 200m 600m 1.00 ireso in amperes plot4 4 2.01m 2.03m 2.05m 2.07m 2.09m time in seconds ?10.0 0 10.0 20.0 30.0 i(cout1) in amperes plot5 5 figure 20. typical waveforms obtained by a spice simulation of the quasi?resonant converter icout ? rms = 5.72a icreso ? rms = 223ma id sec ? rms = 5.02a icoil ? rms = 571ma idrain ? rms = 465ma output capacitor: this component will be selected based on the required output ripple but also on its ability to sustain the total rms current. the dissipation of the capacitor is dictated by its equivalent series resistor (esr) and follows the following formula: pcap = r esr x iripple 2 . a 5.7 a rms current will thus be the primary criterion when selecting the right device. it is also possible to wire capacitors in parallel to split the total current between devices. final schematic figure 21 shows the final schematic implemented in the ncp1205 demoboard. as you can see, the large capacitor placed on the drain allows us to avoid a costly and noisy rcd clamping network. however, the pcb layout offers the necessary place to include one if experiments are needed. the auxiliary winding is wired to offer a stable flyback voltage but a diode (d5) is placed in series with ground to generate the right forward polarity (see figure 15). because of the resonating capacitor placed between drain and ground, a spike can occur at high line as soon as the zvs effect is lost. to help the leb circuitry inside the ncp1205, an additional cleaning network is added through r2?c2. please note that the resonating capacitor c14 is wired between drain and ground and not between drain and source. this is to avoid any negative current flowing inside the current sense pin at turn?off (during the natural drain?source ringing). the feedback loop is standard and uses a tlv431 to further lower the secondary side standby power. since its minimum operating current is 100 a, there is no need to waste 1.0 ma in it as with traditional tl431 series.
and8129/d http://onsemi.com 14 universal input r16 1 meg not wired 10 r14 3 w 220 f c1 x2 2 x 27 mh cm l4 schaffner rn114?08/02 b1 2kbp08m c12 47 f/ 400 v + 1 8 5 34 7 6 2 ncp1205 r32 6.8 k r31 6.8 k ic4 r19 100 k cclamp rclamp dclamp optional network d3, d5 = 1n4148 d3 r1 00 r15 2.2 k d5 c13 82 pf r21 3.3 k 1.5 nf/1 kv c14 wymafkp1 1000 v r20 33 r2 1 k c2 220 pf optional network m2 800 v/4 a mbr20100 d7 t1 + 1000 f/25 v c15/c16/c17 r22 1 k lp = 1.2 mh 1:0.06 (power) 1:0.06 (aux.) + 220 f/ 25 v c19 13.5 v @ 2.5 a ground r24 39 k c18 6.8 nf 18 k r23 r30 3.9 k ic6 tlv431 c23 2.2 nf y1 type r26 1.2 r25 1.2 ic5 sfh6156?2 + 47 f/ 25 v c22 c20 1 nf 18 k r17 figure 21. the final electrical diagram of the ncp1205?based demoboard coilcraft pcv?2?103?05 l3 10 h
and8129/d http://onsemi.com 15 the use of a tlv431 really reduces the output power wasted in no?load. but sometimes, the repetition rate of the switching pulses in standby is so low, that the auxiliary goes down and reaches the ncp1205 uvlolow, restarting the high?voltage current source. to avoid this situation, you either need to increase a bit the auxiliary turn ratio (this is not a problem because the extended vcc range offers that flexibility) or slightly load the output by a resistor. experience has shown that when the auxiliary vcc was close to 8.2 v, a simple 10 mw bleeding element connected to vout was enough to bring vauxiliary to around 9.0 v, giving the necessary headroom. demoboard performance and typical waveforms the 30 w demoboard is available from on semiconductor. it corresponds to figure 21 sketch. below are some shots and measurements captured on the board, testifying for its good characteristics: efficiency @ 230 vac = 86.6% standby power (pout = 0) = 174 mw efficiency @ 110 vac = 84.4% standby power (pout = 0) = 65 mw figure 22. drain?source signals at different powers: p1 p2 p3 p4, you can note the multiple valley jumping. p4 p3 p2 p1 figure 23. at high line and nominal power, the drain level is kept below the mosfet breakdown.
and8129/d http://onsemi.com 16 figure 24. at high line, an output short circuit does not jeopardize the mosfet's life. figure 25. an output bang?bang test (1 to 2.5 a) does not reveal any instability. the spikes are related to the lc filter installed on the output.
and8129/d http://onsemi.com 17 bill of materials all resistors are 1/4 w 5% smd unless otherwise noted. part value designator type manufacturer reference comments 00 r1 1.0 k r2 10 r14 2.2 k r15 18 k r17 100 k r19 33 r20 through holes 18 k r23 1.2 r26 1.0 w 1.2 r25 1.0 w 3.3 k r21 1.0 k r22 39 k r24 3.9 k r30 6.8 k r31 through holes 6.8 k r32 through holes 220 nf c1 220 pf c2 47 f/400 v c12 snap?in bc comp. 2222?057?56479 82 pf c13 1.5 nf/1.0 kv c14 wima 1500?fkp1 1000 f/25 v c15 vertical 1000 f/25 v c16 vertical 1000 f/25 v c17 vertical 6.8 nf c18 220 f/25 v c19 1.0 nf c20 47 f/25 v c22 2.2 nf c23 roederstein wy series y1 10 h l3 coilcraft pcv?2?103?05 2 x 27 mh l4 schaffner rn114?08/0.2 bridge d8 kbu?8j mbr20100 d7 on semiconductor stp5nb80 m2 st ncp1205p ic4 on semiconductor sfh6156?2 ic5 infineon tlv431 ic6 on semiconductor to?92 30 w transformer t1 coilcraft z9508?a pulse?engineering pf0137
and8129/d http://onsemi.com 18 transformer vendor details pulse engineering site d'orgelet zone industrielle 39270 ? orgelet tel.: 33 (0)3 84 35 04 04 fax: 33 (0)3 84 25 46 41 http://www.pulseeng.com/ email: vpelletier@pulseeng.com coilcraft 1102 silver lake road cary, illinois 60013 usa tel.: (847) 6396400 fax: (847) 6391469 email: info@coilcraft.com http://www.coilcraft.com on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 and8129/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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